0.1nm Engineering, and Optimizing Non-Differentiable Code

Why I'm writing this

Samsung Electronics' memory division. The place that overcomes physical limits at the 0.1nm scale and produces things like HBM. But behind the glamorous specs, what's actually happening is...

Thousands of MS/PhD engineers running overnight simulations to close Verilog timing, and wrestling with regexes to find a particular hex value in terabytes of logs. The extreme end of what you'd call human-in-the-loop optimization.

I want to work through why introducing AI agents into semiconductor design/verification is inevitable, and how that optimizes "non-differentiable code."

The bottleneck on the ground: it isn't writing code, it's translating specs

70% of memory semiconductor development isn't creative design. It's the translation and validation process of converting vast specs (JEDEC, internal specs) into RTL code and verifying that the conversion is correct.

I looked at what happens when an agentic tool like Claude Code enters that.

Case 1: RTL design (parameter mapping & FSM logic)

Designing a DRAM controller, when the spec changes you have to modify the timing parameters (tRFC, tREFI, etc.) and the state machine logic. Simple, and the single biggest source of human error.

[Before: human engineer] The engineer puts the PDF on a second monitor, calculates clock cycles on a calculator, and hardcodes them. Make a mistake and you burn days debugging.

[After: agentic workflow] Tell the agent: "Referencing DDR5 Spec Rev 1.2, redesign the refresh FSM for 3200MHz."

// Generated by Agent (Context: DDR5 Spec Rev 1.2, Target: 3200MHz)
module dram_refresh_ctrl (
    input logic clk,
    input logic rst_n,
    output logic ref_req
);
    // [Agent Insight] tREFI 3.9us at 3200MHz (Period: 0.3125ns)
    // 3900ns / 0.3125ns = 12480 cycles
    localparam int REF_PERIOD_CYCLES = 12480;

    // Timer Logic
    logic [13:0] timer; // Agent optimizes bit-width too (14 bits is enough for 12480)

    typedef enum logic [1:0] {IDLE, COUNT, REQ_ASSERT, WAIT_ACK} state_t;
    state_t current_state, next_state;

    // FSM State Logic (omitted: agent generates it per spec)
    // ...
endmodule

The agent doesn't just write code — it leaves the derivation for REF_PERIOD_CYCLES as a comment and optimizes the timer bit width to reduce wasted area at synthesis. That part was impressive.

Case 2: Verification (UVM sequence for corner cases)

A verification engineer's time mostly goes into "how do I break this design."

[Before: human engineer] Analyze the coverage report and hand-write sequences to fill the holes that haven't been hit.

[After: agentic workflow] Tell the agent: "Coverage is 92%. Write a sequence mixing random writes/reads under bank conflict to fill the hole."

// Generated by Agent (Objective: Maximize Bank Conflict Coverage)
class heavy_conflict_sequence extends uvm_sequence #(mem_transaction);
    `uvm_object_utils(heavy_conflict_sequence)

    task body();
        mem_transaction tr;
        int prev_bank = -1;

        repeat(5000) begin
            tr = mem_transaction::type_id::create("tr");
            start_item(tr);
            if (!tr.randomize() with {
                // [Agent Insight] force the same bank as the previous transaction → induce conflict
                if (prev_bank != -1) { bank == prev_bank; }
                // different row address → induce page miss
                row_addr inside {[0:32'hFFFF]};
                op_type dist {WRITE:=60, READ:=40};
                delay == 0; // back-to-back to maximize pipeline pressure
            }) begin
                `uvm_error("SEQ", "Randomization failed")
            end
            prev_bank = tr.bank;
            finish_item(tr);
        end
    endtask
endclass

Understanding the abstract intent "bank conflict" and converting it into concrete constraints to induce it works quite well.

Why only now

Why couldn't decades of automation tooling do this, and why do LLM-based agents solve it? I think it comes down to the discontinuity of code.

Semiconductor development is one giant simulated annealing process

It occurred to me that the development process resembles annealing.

1. Global search (high temperature): the architect makes big structural changes — "HBM4 is a 16-high stack," "the process is 1c nm."
2. Local optimization (cooling): thousands of engineers fine-tune parameters to hit PPA targets.

The limits of existing algorithms

The problem is that local optimization stage. Physical quantities (voltage, length) are differentiable, so existing algorithms optimize them easily. But code (RTL/scripts) is not differentiable.

• Change 5 to 5.1 in if (cnt > 5) and it's a syntax error.
• Existing mechanical search (GA and friends) couldn't search a "code space" where syntax and meaning are coupled.
• So the only executor that could "modify code within the syntax while achieving the intent" was the human engineer.

LLMs: the beginning of semantic optimization

LLM-based agents are different, I think, because they handle code in a space of meaning rather than as text.

• They understand a semantic instruction like "there's a setup time violation, add a buffer to the data path."
• They convert that into syntactically perfect code.
• In other words, the discontinuous space of code has become differentiable.

Similar currents

This shift isn't only about semiconductors. The inverse-design current of "abandon the perfect formula, find the optimal approximation" shows up across fields.

Bio: DeepMind AlphaFold

Solving protein structure with physics (the Schrödinger equation) would take about the age of the universe.

AlphaFold threw out the physics. It learned patterns from 200,000 protein structures and predicted structure to 99% accuracy without experiments.

Semiconductor: Google AlphaChip

Floorplanning inside a chip depended on human engineers' intuition for decades.

AI treated chip design like Go and did reinforcement learning. The output was a bizarre-looking layout to human eyes, but in simulation the power efficiency and performance crushed human designs.

Aerospace: SpaceX

Instead of NASA's approach of spending years drawing a perfect blueprint, it chose iterative design.

3D print prototypes fast, analyze test data with AI, and fly a revised version the next day.

Filing it here for now

I get the sense the engineer's role is shifting from "the person who implements the spec as code" to "the person who defines the problem and verifies the physical validity of what the AI produces."

Security concerns keep it locked inside internal networks for now, but the pressure of technical efficiency will eventually push over that dam.

"The formula is dead, the approximation won."

Time to say goodbye to the era of grinding man-hours and get ready to explore the 0.1nm limit with a new colleague called the agent. That's how I'm seeing it, anyway.